1. Field of the Invention
The present invention generally relates to a signal processing circuit and a signal processing method, and more particularly, to a signal processing circuit and a signal processing method that convert a frequency modulation signal into digital data.
2. Description of the Related Art
FIG. 6 is a block diagram showing the structure of an optical disk drive.
The optical disk drive 100 shown in FIG. 6 is a CD-R drive, for example, on which a CD-R disk 40 is set. Information is recorded in, and read out of, the CD-R disk 40.
The optical disk drive 100 is configured by an optical system 41, a spindle motor 42, a sled motor 43, a laser driver 44, a front monitor 45, an auto laser power control (ALPC) circuit 46, a recording compensation circuit 47, a wobble signal processing unit 48, an RF amplifier 49, a focus/tracking servo circuit 50, a radial servo circuit 51, a spindle servo circuit 52, a CD encoding/decoding circuit 53, a D/A converter 54, an audio amplifier 55, RAMs 56 and 58, a CD-ROM encoding/decoding circuit 57, an interface/buffer controller 59, and a CPU 60. The optical disk drive 100 performs recording and reading out of data in response to a command sent by a host computer 61.
The spindle motor 42 controlled by the spindle servo circuit 52 rotates the optical disk 40 at a predetermined rotational speed. The optical system 41 is facing the optical disk 40. The optical system 41 records data by emitting a laser beam to the optical disk 40, or reads out the data by detecting a reflectional laser beam from the optical disk 40. The sled motor 43 and the focus/tracking servo circuit 50 control the position of the laser beam emitted to the optical disk 40.
The sled motor 43, which is controlled by the radial servo circuit 51, actuates a carriage, part of the optical system 41, in the radial direction. The focus/tracking servo circuit 50 controls a focus actuator and a tracking actuator (both not shown) of the optical system 41.
The read signal outputted from the optical system 41 is provided to the RF amplifier 49. The RF amplifier 49 amplifies the read signal. The read signal, after being separated into servo signals of different kinds, is provided to the CD encoding/decoding circuit 53 as a main signal. The servo signals are provided to each servo circuit.
The CD-ROM encoding/decoding circuit 57 performs operations such as encoding and decoding of the error correction coding (ECC) that is unique to the CD-ROM, and detecting a header. The RAM 56 provides the CD-ROM encoding/decoding circuit 57 with a working memory area. The interface/buffer controller 59 exchanges data with the host computer 61 and controls a data buffer. The RAM 58 provides the interface/buffer controller 59 with a working memory area.
In the case that the optical disk 40 is an audio disk, the read signal decoded by the CD encoding/decoding circuit 53 is transferred to the D/A converter 54 for the conversion into an analog signal, and amplified by the audio amplifier 55.
The CPU 60 controls the entire operation of the optical disk drive.
FIG. 7 is a schematic sectional view showing the structure of an optical disk.
As shown in FIG. 7, a wobble 40b is formed along each track 40a on the CD-R disk 40 in advance. A wobble signal is obtained by detecting the wobble 40b. The wobble signal, which is modulated in FM, contains control information of different kinds, such as an address indicating a position in the optical disk 40. The control information is obtained by demodulating the FM signal obtained by detecting the wobble 40b. In order to obtain correct information such as an address, it is necessary to convert the wobble signal modulated in FM into digital data.
FIG. 8 is a block diagram showing a conventional signal processing circuit as an example. FIGS. 9 (A)-(D) are waveforms of the conventional signal processing circuit.
The signal processing circuit 500 shown in FIG. 8 is configured by a rise/fall edge detecting circuit 501, a counter circuit 502, a latch circuit 503, and a digital low pass filter (LPF) 504.
The rise/fall edge detecting circuit 501 is provided with an FM signal shown in FIG. 9 (A) inputted through an FM signal terminal 505. The rise/fall edge detecting circuit 501 compares the FM signal with the zero level, and generates an FM pulse signal shown in FIG. 9 (B) that is at a high level if the FM signal is higher than the zero level, and at a low level if the FM signal is lower than the zero level. The rise/fall edge detecting circuit 501 further generates a rise/fall edge signal shown in FIG. 9 (C) by detecting rise edges and fall edges of the FM pulse signal. The rise/fall edge signal is provided to the counter circuit 502, the latch circuit 503, and the digital LPF 504.
The counter circuit 502 is cleared in response to reception of the rise/fall edge signal sent from the rise/fall edge detecting circuit 501, and counts the clock signals provided through a clock signal terminal 506. The count of the counter circuit 502 changes as shown in FIG. 9 (D), and is provided to the latch circuit 503.
The latch circuit 503 is provided with the count of the counter circuit 502 and the rise/fall edge signal of the rise/fall edge detecting circuit 501, and latches counts Q1-Qn in response to the rise/fall edge signal. The counts latched as Q1-Qn are sent to the digital LPF 504.
The digital LPF 504 is provided with the counts of the latch circuit 503 and the rise/fall edge signal of the rise/fall edge detecting circuit 501. The digital LPF 504 eliminates noise in the FM signal as a digital low pass filter based on the counts provided by the latch circuit 503. A digital FM signal, after being processed by the digital LPF 504, is outputted from digital FM signal terminal 507. The digital FM signal is demodulated and the control information contained in the digital FM signal is extracted.
However, the actual FM signal contains significant noise.
With reference to FIGS. 10, 11 (A)-(D), and 12 (A)-(C), the operation of the conventional signal processing circuit is further described.
As shown in FIG. 10, the actual FM signal crosses across the zero level several times as it passes through the zero level region due to the noise. If the actual FM signal is converted into an FM pulse signal without any countermeasure for noise reduction, undesirable pulses, or chattering noise, is generated before and after the true FM pulse signal, as shown in FIG. 11 (A). Because of the generation of these undesirable pulses (chattering noise), a plurality of undesirable rise/fall edges are generated as shown in FIG. 11 (B). The counter circuit 502 counts, in response to these undesirable rise/fall edges, the clock signal. It is impossible to obtain an accurate FM pulse signal in this situation.
[Conventional Technique]
A method for detecting the rise/fall edges of the FM pulse signal, by excluding time periods in which chattering noise is generated, has been proposed. The method will be described with reference to FIG. 12 below.
FIG. 12 is waveforms showing a conventional method for eliminating the noise. FIG. 12 (A) is a waveform of an inputted FM pulse signal; FIG. 12 (B) is a waveform of the FM pulse signal after noise-reduction; and FIG. 12 (C) is a waveform of the rise/fall edge signal of the pulse signal after noise reduction.
In a conventional technique, an edge is identified subject to the level of an FM pulse signal remaining at the same level for a predetermined time period T3. The FM pulse signal rises to a high level at time t1, but it falls to a low level within the predetermined time period T3. It is assumed in this conventional technique that the rise edge of the FM pulse signal at time t1 is generated by noise, and accordingly this rise edge is ignored. However, the FM pulse signal rises to a high level at time t2, and it remains at the high level for more than the predetermined time period T3 after the time t2. The rise edge of the FM pulse signal at time t2 is considered to be a true edge that is not caused by noise. The rise edge of the FM pulse signal at time t7 is also identified as a true edge of the FM pulse signal.
Likewise, the FM pulse signal falls at time t4 but it rises before the predetermined time period T3 passes. Accordingly, the fall edge is ignored. The fall edges at time t5 and t9 are identified as true edges because they remain at a low level for more than the predetermined time T3.
The rise/fall edge signal after eliminating the noise contained in the FM pulse signal, as shown in FIG. 12 (C), is obtained by the conventional technique.
As described above, the FM pulse signal contains noise that results in rise and fall in the FM pulse signal. If the edges caused by the noise are detected, and the clock signal is counted even during the interval between the edges, a count based on the noise is outputted. Accordingly, the digital FM signal cannot be reproduced due to the effect of the noise.
The conventional technique to eliminate the noise is a method in which an edge is ignored unless the FM pulse signal remains at the same level for a predetermined time period T3 after the edge appears. The conventional technique, however, causes a delay in detecting edges. If the FM pulse signal is noisy as shown in FIG. 12 (A), the first rise edge in the FM pulse signal after conventional noise reduction shown in FIG. 12 (B) is detected at time t3. The noise causes a delay of time Tx. Similarly, the first fall edge in the FM pulse signal after conventional noise reduction is detected at time t6 after a delay of Ty. Both Tx and Ty are longer than T3. The second rise edge in the FM pulse signal after conventional noise reduction, however, is detected at time t8. Because noise does not affect the detection of this rise edge, the delay in detecting the rise edge at time t8 is T3, that is, the predetermined time period. Likewise, the second fall edge in the FM pulse signal after conventional noise reduction is detected at time t10 after the delay of T3. The amount of noise affects the delay Tx and Ty, and causes fluctuation in the rise/fall edge signal.
Accordingly, it is a general object of the present invention to provide a novel and useful signal processing circuit and a signal processing method in which the problem described above is eliminated.
Another and more specific object of the present invention is to provide a signal processing circuit and a signal processing method for accurately detecting a time period in which an input pulse signal remains at a high level and/or at a low level by eliminating noise contained in the input pulse signal.
To achieve one of the objects, a signal processing circuit for converting an input signal containing chattering noise therein into an output signal, according to the present invention, includes: a first accumulative timer that starts, in response to a change in the input signal from a first input level to a second input level, measuring a first time period in which the input signal is at the second input level; sends a first signal when the first time period reaches a first predetermined time, and is reset in response to a first change in the output signal from a first output level to a second output level, and a signal generator that turns, in response to the first signal sent by the first accumulative timer, the output signal to the second output level.
The signal processing circuit according to the present invention measures, by using the accumulative timer, a time period in which the input signal is at a high (low) level until the first predetermined time passes, and turns the output signal to a high (low) level by activating the signal generator. The accumulative timer is reset at the same time.
The accumulative timer accumulates only the time period in which the input signal is at a high (low) level, but disregards the time period in which the input signal is at a low (high) level. Consequently, the pulse signal that is outputted by the signal generator has a pulse width that is equal to the total width of high (low) level pulses including the high (low) level pulses caused by the chattering noise. In other words, the pulse signal that is outputted by the signal generator is an imaginary pulse that is formed by gathering all high (low) level pulses.
The pulse width of the imaginary pulse described above is substantially equal to the pulse width of the true FM pulse signal having no chattering noise therein.
The chattering of the pulse signal that is outputted by the signal generator can be avoided by delaying the rise (fall) of the pulse signal by the first predetermined time period until the chattering noise of the input signal stops. The first predetermined time period is determined in consideration of the noise level contained in the input signal.
To handle both high and low levels, the signal processing circuit according to the present invention further includes a second accumulative timer that starts, in response to a change in the input signal from the second input level to the first input level, measuring a second time period in which the input signal is at the first input level, sends a second signal when the second time period reaches a second predetermined time, and is reset in response to a second change in the output signal from the second output level to the first output level, wherein the signal generator turns, in response to the second signal sent by the second accumulative timer, the output signal to the first output level, and the first predetermined time and the second predetermined time are determined in connection with a duty ratio of the first input level and the second input level.
Because the first predetermined time and the second predetermined time can be determined independently, the duty ratio of the pulse signal outputted by the signal generator can be set in accordance with the properties of the input signal.
The present invention can be represented as a signal processing method for converting an input signal having chattering noise therein into an output signal, including a step of starting a first accumulative timer in response to a change in the input signal from a first input level to a second input level, a step of measuring a first time period in which the input signal is at the second input level, a step of informing a signal generator whether a first predetermined time has passed, a step of turning the output signal to the second output level in response to information that the first predetermined time has passed, and a step of resetting the timer in response to a change in the output signal from the first output level to the second output level.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.